The present subject matter relates generally to semiconductor device manufacturing and, more particularly, to a method and apparatus for simulating gate capacitance of a tucked transistor device.
The fabrication of complex integrated circuits involves the fabrication of a large number of transistor elements, which are used in logic circuits as switching devices. Generally, various process technologies are currently practiced for complex circuitry, such as microprocessors, storage chips, and the like. One process technology currently used is complimentary metal oxide silicon (CMOS) technology, which provides benefits in terms of operating speed, power consumption, and/or cost efficiency. In CMOS circuits, complementary transistors (e.g., p-channel transistors and n-channel transistors) are used for forming circuit elements, such as inverters and other logic gates to design complex circuit assemblies, such as CPUs, storage chips, and the like.
During the fabrication of complex integrated circuits using CMOS technology, millions of transistors are formed on a substrate including a crystalline semiconductor layer. A transistor includes pn-junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. A conductive channel is formed when an appropriate control voltage is applied to the gate electrode. The conductivity of the channel region depends on the dopant concentration, the mobility of the majority charge carriers, and—for a given extension of the channel region in the transistor width direction—on the distance between the source and drain regions, which is also referred to as channel length.
Hence, the overall conductivity of the channel region substantially determines an aspect of the performance of the MOS transistors. By reducing the channel length, and accordingly, the channel resistivity, an increase in the operating speed of the integrated circuits may be achieved.
The continuing shrinkage of the transistor dimensions does raise issues that might offset some of the advantages gained by the reduced channel length. For example, highly sophisticated vertical and lateral dopant profiles may be required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for obtaining a high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation of current process techniques and possibly the development of new process techniques. One technique for enhancing the channel conductivity of the transistor elements involves increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is to modify the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of p-type transistors.
The introduction of stress or strain engineering into integrated circuit fabrication is a promising approach for future device generations. Strained silicon may be considered as a “new” type of semiconductor material that enables the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials and also allows the use of many of the well-established current manufacturing techniques.
One technique for inducing stress in the channel region involves introducing, for instance, a silicon/germanium layer next to the channel region so as to induce a compressive stress that may result in a corresponding strain. The transistor performance of p-channel transistors may be considerably enhanced by the introduction of stress-creating layers next to the channel region. For this purpose a strained silicon/germanium layer may be formed in the drain and source regions of the transistors. The compressively strained drain and source regions create uni-axial strain in the adjacent silicon channel region. When forming the Si/Ge layer, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked. Subsequently, the silicon/germanium layer is selectively formed by epitaxial growth. For generating a tensile strain in the silicon channel region, Si/C may be used instead of SiGe.
FIGS. 1A and 1B show a cross-sectional view, and a top view, respectively of a semiconductor device 100 in an early manufacturing stage. The semiconductor device 100 comprises a semiconductor layer 105 of a first semiconductor material in and/or on which circuit elements, such as transistors, capacitors, resistors, and the like may be formed. The semiconductor layer 105 may be provided on a substrate (not shown), e.g. on a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate, wherein the semiconductor layer 105 may be formed on a buried insulation layer. The semiconductor layer 105 may be a silicon-based crystalline semiconductor layer comprising silicon with a concentration of at least 50%. The semiconductor layer 105 may represent a doped silicon layer as is typically used for highly complex integrated circuits having transistor elements with a gate length around 50 nm or below.
Gate electrodes 110 may be formed above the semiconductor layer 105. The gate electrodes 110 are functional devices, or switching gate electrodes. The gate electrodes 110 may be formed of doped polysilicon or other suitable material which is provided above the semiconductor layer 105 and is separated therefrom by a gate insulation layer 115. The first semiconductor material 105 forms a channel region 120 for a finished transistor. Sidewalls of the gate electrodes 110 may be provided with disposable sidewall spacers (not shown). The disposable sidewall spacers may consist of any appropriate dielectric material, such a silicon nitride, silicon dioxide, or mixtures thereof.
The semiconductor device 100 of FIG. 1A further comprises a cavity or recess defined in the semiconductor layer 105 that is filled with a strained material and doped to define a diffusion region 130. The gate electrode 110 may be used as an etch and growth mask in an etch process and an epitaxial growth process for the formation of the embedded strained semiconductor material. The regions are doped during the growth and/or by implantation to define source and drain regions for the device 100. Silicide contact regions (not shown) may also be defined in a surface portion of the diffusion region 130. Contact elements 135 may be embedded in an interlayer dielectric layer 140 for contacting the underlying diffusion regions 130.
It is common to segregate various regions of the device 100 using isolation structures, as illustrated by an isolation structure 145 defined in the layer 105. Typically, the isolation structure 145 is a trench filled with a dielectric material. To maintain the spacing approximately equal across different regions of the device 100, one or more non-functional gate electrodes 110′ may be formed. In FIG. 1B, the gate electrode 110′ is formed above the isolation structure 145. The diffusion region 130′ laterally abuts the isolation structure 145. The geometry and material of the isolation structure 145 affects the etch and growth processes for forming the embedded strained material, so the diffusion region 130′ is reduced in size as compared to the diffusion regions 130 that are defined by adjacent gate electrodes 110. This material loss causes a decrease in performance for the device 100.
One technique for addressing the strained material losses adjacent isolation structures is to partially overlap the non-functional gate electrode structures 110′ with the isolation structure 145 so that the etch boundary for forming the diffusion regions 130 is defined by the gate electrode 110′ rather than the isolation structure 145. This approach is referred to as a tucked design, and is illustrated by the tucked device 200 shown in the cross-section and top views of FIGS. 2A and 2B.
An issue that arises from a tucked structure is that the gate electrode 110′ is partially over the diffusion region 130′ of the adjacent transistor structure, rather than being completely over the isolation structure 145. In this arrangement, the gate electrode 110′ acts as a floating gate electrode, thereby affecting the operation of the adjacent transistor.
In semiconductor manufacturing, simulation techniques are employed to predict the operation of the designed devices prior to actual fabrication. Device models are used to represent the various devices in a die layout. The models are used to generate performance parameters for the devices and to simulate their operation.
FIG. 3 illustrates a conventional tucked transistor model 300 for the tucked device 200. The model 300 includes a field effect transistor (FET) sub-circuit 305 including a gate bound diode 310, an area diode 315, and a floating gate bound diode 320. A substrate diode 325 is also included as a separate sub-circuit in the model 300. To model the effects of the floating gate electrode 110′ an additional floating gate sub-circuit 330 is provided in the model 300. The floating gate sub-circuit 330 includes a first resistor-capacitor (RC) pair including a resistor 335 for modeling gate to diffusion region leakage and a capacitor 340 for modeling gate to diffusion region capacitance. A second RC pair includes a resistor 345 for modeling gate to well leakage and a capacitor 350 for modeling gate to well capacitance.
The floating gate sub-circuit 330 adds complexity to the overall device model 300 by requiring additional components in the netlist. The values for the components of floating gate sub-circuit 330 may be implemented using fixed values, which may be inaccurate, or by using bias-dependent values, which add complexity.
Another limitation of the conventional model 300 shown in FIG. 3 is that in an actual device, the gate bound diode 310 junction capacitance is approximately 5-12 times larger than the STI bound diode 320 junction capacitance. The difference could potentially be further increased due to dopant out-diffusion near the isolation structure 145. The conventional model 300 fails to capture this aspect of the tucked device 200.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.